Schematic Design of Two-Stage Op-Amp

This is the term project of the EL-303 Analog integrated circuit course. In this document my objective is to implement a Two-Stage Op-Amp circuit with RC compensation in the Cadence environment. Building blocks are divided in four parts, I have documented extra laboraory assignments for the future reference. For more info please download the attachment. Here are the design specifications for the amplifier:

  • Avo >80dB

  • GBW > 10MHz

  • SR > 5V/us

  • PM > 60deg

  • Ptot < 500uW (includes biasing currents)

  • PSRRdd > 40dB (for f<200kHz)

  • PSRRss > 40dB (for f<200kHz)

  • Load: CL=10pF


January 2015


Analog Circuit Design.

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